Elmore delay is a simple approximation to the delay through an RC network in an electronic system.
For tree structured networks, find the delay through each segment as the R (electrical resistance) times the downstream C (electrical capacitance). Sum the delays from the root to the sink.
The Elmore delay analysis model estimates the delay from a source (root) to one of the leaf nodes as the sum of the resistance in the path to the ith node multiplied by the capacitance present at the end of the branch. It provides a simplistic delay analysis that avoids time-consuming numerical integration/differential equations of an RC network.
In other words, the propagation delay from a switching source (root) to an ith branch node is given as the product of the capacitance “Ci” of the node with the sum of the resistance from the source to the node, Ris.
The Elmore delay for Vout is given as tpd = R1C1+(R1+ R2)C2
